Static random access memories (SRAMs) typically include one or more arrays of memory cells, with each cell including a pair of cross-coupled active storage devices. The storage devices are typically transistors, for example insulated gate field effect transistors (referred to herein as "MOS" transistors). Each cross-coupled pair of transistors is disposed between opposite power supply nodes and can be latched in one of two states depending upon which of the two storage devices is turned on. The cross-coupled arrangement results in complementary signals at two data nodes, both (or one) of which can be read by a pair of bit lines (or single bit line) by another pair of access active devices. The access devices are usually driven by a word line. Commonly, in addition to the two cross-coupled storage devices and two access devices, current limiting devices are also provided to reduce the amount of current consumed by the "on" storage device. A current limiting device is situated between each storage device and one of the power supply nodes. This SRAM cell approach, as described, has given rise to "four transistor" (4-T) memory cells and "six transistor" (6-T) memory cells. In the case of 4-T cells, the current limiting devices are typically resistors.
For 6-T cells, the current limiting devices are typically another pair of active devices.
The memory cells of conventional SRAM arrays are arranged in rows and columns. Cells within the same row have access devices driven by the same word line. Cells within the same column are coupled to the same bit lines. When a word line is activated, the access devices couple the data nodes to bit lines, which in turn, provide output data in a read operation, or are driven by write data in a write operation.
A schematic diagram of a prior art 4-T cell is illustrated in FIG. 1. The 4-T cell is designated by the general reference character 10. The N-channel MOS (NMOS) transistors T1 and T2 are cross-coupled storage devices that form a latching structure. The drains of the transistors T1 and T2 form complementary data nodes 12a and 12b. The data nodes 12a and 12b are coupled to the bit lines (not shown in FIG. 1) by the NMOS transistors T3 and T4. As is well-known in the art, the gates of the transistors T3 and T4 are commonly driven by a word line (not shown). The sources of the transistors T1 and T2 are commonly coupled to a first power supply, Vss (ground), while the data nodes 12a and 12b are coupled to a second power supply, Vcc, through the current limiting devices (resistors R1 and R2). It is desirable for the resistors R1 and R2 to have high impedances to limit power consumption.
As is well known in the art, the resistors R1 and R2 are typically fabricated from doped polysilicon when included within an integrated circuit. A graph of the resistivity of moderately doped polysilicon versus the concentration of the dopant is illustrated in FIG. 2. The curve 20 illustrates the relationship between the concentration of dopant within the polysilicon and the corresponding resistivity of the doped polysilicon. As illustrated by the curve 20, as the concentration of dopant is increased, the resistivity of the doped polysilicon decreases.
A high activation energy is required for a typical polysilicon resistance sheet with a high load resistance due to a lower concentration of dopant in the resistance sheet. This high activation energy causes problems at low temperatures. There is also a large variation in the sheet resistance of doped polysilicon due to fluctuations in the grain size, thereby limiting the manufacturability of devices. Because of these problems, the application of polysilicon loads is typically limited to a sheet resistance of approximately 500 Gohm/sq at room temperature. Accordingly, in order to provide a high load resistance for such polysilicon loads, it is required to use a sheet having a large length/width (L/W) ratio for a given thickness. However, the available area for such a sheet is generally fixed due to packaging, size, manufacturing and cost constraints.
In order to obtain a greater L/W ratio, the width of a resistance sheet cannot be arbitrarily reduced due to manufacturing requirements of conventional semiconductor processes as well as for current carrying capability of the resistance sheet. Accordingly, to increase the L/W ratio for a given resistance sheet, and thereby increase the load resistance of the resistance sheet, the length of the resistance sheet must typically be increased. This requires additional space on the silicon substrate and increases the overall die dimensions of an SRAM.
Another approach used to increase the load resistance of the resistance sheet is to lower the implant dose and thereby decrease the concentration of dopant within the resistance sheet. However, this approach requires a higher activation energy, as described above, and leads to manufacturability problems associated with control of the higher activation energy. It is typically preferred to employ a concentration of dopant of the resistance sheet for N-type silicon within the flat region of the curve 20, illustrated by the circle 22 of FIG. 2. Accordingly, in order to obtain a higher resistance value for a given resistance sheet having a fixed width and dopant concentration, the length of the resistance sheet must be increased.
A cross section of the length dimension of a conventional resistance sheet of polysilicon is illustrated in FIG. 3. This resistance sheet 30 is formed over a field oxide region 32 within a silicon substrate. An oxide layer 34 is deposited over the field oxide region 32. This oxide layer 34 is typically deposited by a chemical vapor deposition (CVD) process, as is well known in the art. A layer of doped polysilicon 38 is then formed over the oxide layer 34, thereby forming the resistance sheet. This layer of doped polysilicon 38 is used to form the resistors R1 and R2 in a conventional SRAM array.
As described above, for a given width of the resistance sheet 30 having a fixed dopant concentration, the resistance value of the resistance sheet 30 is dependent on the length of the resistance sheet 30. For a given width of the resistance sheet, the resistance value of the resistance sheet 30 can be increased by increasing the length of the resistance sheet and thereby increasing the L/W ratio of the resistance sheet. However, increasing the length of the resistance sheet 30, increases the overall dimensions of the SRAM array. As illustrated in FIG. 3, the length of the resistance sheet shown is 2.5 micrometers, yielding an effective length of 2.5 micrometers.
What is needed is an SRAM structure with an increased load resistance which does not require an increase of the activation energy or an increase in the necessary silicon area. What is further needed is a fabrication method for an SRAM which increases the load resistance of the resistors R1 and R2, without increasing the necessary activation energy or the necessary silicon area.